1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit design, and more particularly, to a non-abrupt switching mechanism for a sleep transistor of a power gate structure for reducing ground bounce.
2. Description of the Related Art
As the number of devices being packed into a system-on-a-chip (SoC) approaches millions, power consumption has become a critical design concern due to the increasing gap between the energy required by portable computation/communication devices and the energy supplied by the battery. Traditionally, the primary source of power consumption for a CMOS design comes from the switching of logic states. The switching power is expressed asPswitch=a0→1·f·clk(Cload·V2dd) where 0→1 is the average number of times in a clock cycle that a switch from 0 to 1 occurs, fclk is the clock frequency, Cload is the load capacitance and Vdd is the supply voltage.
The equation clearly shows that supply voltage affects power dissipation in a quadratic order. Thus, voltage scaling has been deemed the most effective approach for dynamic power reduction. Reducing Vdd alone, however, causes serious circuit performance degradation. One way to maintain performance is to scale down both Vdd and the threshold voltage Vth of logic transistors. Reducing Vth, however, exponentially increases subthreshold leakage current. This problem escalates in deep-submicron (DSM) technologies. Managing leakage current has become an integral part of overall power management.
Referring to FIG. 1, a multi-threshold CMOS (MTCMOS) circuit 100, including a “power gate structure,” is one of the well-known techniques to reduce leakage power in the standby mode while maintaining high speed in the active mode. The logic gates of a function and storage block 102 of the MTCMOS circuit 100 are implemented using low threshold voltage (LVT) transistors and are sinked to a virtual ground rail (VGND). VGND is linked to the ground rail (GND) through a high threshold voltage (HVT) transistor, called a sleep transistor 104. The sleep transistor 104 is controlled by a TURN-ON signal used for active/standby mode control.
The ground bounce due to switching of a sleep transistor on a power gate structure is analyzed with reference to FIGS. 1-3, where FIG. 2 is a graph illustrating the I-V characteristics for a NMOS sleep transistor operated in linear, saturation and cut-off modes and FIG. 3 illustrates a sleep transistor in a power gate structure modeled as (a) a resistor, (b) an opened switch and (c) a practical current source. The problem caused by the ground bounce will also be described.
During the active mode, the sleep transistor 104 of the power gate structure 100 in FIG. 1 operates in its linear region of FIG. 2. The sleep transistor may be modeled as a resistor R as shown in FIG. 3(a). Here, the sleep transistor generates a small voltage drop Vx equal to Iactive×R, where Iactive is the total current demand of the logic block 302 operating in active mode. In DSM technologies, the supply voltage is scaled down aggressively, causing the resistance of the sleep transistor to increase dramatically, requiring larger size sleep device.
In standby mode, the sleep transistor operates in the cutoff region of FIG. 2 and may be modeled as an opened switch 330 as shown in FIG. 3(b). During this mode, the leakage current is limited by the sleep transistor, which is reduced by a high threshold and a proportionally smaller width. By turning off the sleep transistor during the sleep period, the VGND rail is charged up to a steady state value near VDD.
As the sleep transistor is turned on, charge trapped in capacitive loads of the logic block 302 and virtual ground rail VGND begins to discharge through the sleep transistor. Initially, the sleep transistor operates in the saturation region of FIG. 2 and may be modeled as a practical current source 332 as shown in FIG. 3(c). The amount of current that can flow through the sleep transistor at this moment is much larger than the active mode current, Iactive.
FIG. 4 shows that the instantaneous current creates inductively induced voltage fluctuation in the VDD and GND rails. L, C, and R are the parasitic inductance, capacitance, and resistance of the GND rail, respectively.
Ground bounce, also known as simultaneous switching noise (SSN), is a voltage glitch induced in supply distributions due to changing currents passing through either wire/substrate inductance or package lead inductance associated with power or ground rails. These voltage glitches or surge/droop phenomena increase when larger current changes occur in a shorter period of time, which is a feature of turning on the sleep transistor. If the magnitude of this voltage surge/drop is greater than the noise margin of a circuit, the circuit may erroneously latch the wrong value or switch at the wrong time.
In previous technologies, switching of input/output buffers and internal circuitry were the primary sources of ground bounce. In designs employing a power gate structure to control leakage power, however, ground bounce due to switching of the sleep transistor is a potential problem. Also, lower supply voltages reduce noise immunity and threshold voltage, which create greater noise sensitivity.